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cs.OS2026
Cross-Core Inference Offload as an Operating-System Service on Dual-Core Microcontrollers
Dimitrios Kafetzis
Dual-core MCUs are asymmetric: on NXP's MCXN947, the second Cortex-M33 has no FPU, DSP extension, TrustZone, or MPU. We treat the asymmetry as a design input in the Phase 3 dual-co…
cs.OS2026
Inference Pipelines as Operating-System Objects: Priority Scheduling and Constant-Footprint Streaming for Microcontroller Neural Inference
Dimitrios Kafetzis
Microcontroller runtimes treat the inference pipeline -- pre-processing, accelerator invocation, post-processing -- as application code: every project re-implements stage sequencin…