1 citations · 1 across the 2 of their papers we have counts for
3 papers
cs.AR2026
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Lik Tung Fu, Jie Zhou, Shaokai Ren +6
Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced sim…
cs.AR2025
ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
Runkai Li, Jia Xiong, Xiuyuan He +5
High-Level Synthesis (HLS) improves IC development productivity by enabling hardware design from C-like languages. However, strict coding constraints and design-specific optimizati…
cs.AR2025★ 1 cited
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs
Runkai Li, Jia Xiong, Xi Wang
High-Level Synthesis (HLS) serves as an agile hardware development tool that streamlines the circuit design by abstracting the register transfer level into behavioral descriptions,…