22 citations · 22 across the 3 of their papers we have counts for
3 papers
cs.CR2026
PVAC: A RowHammer Mitigation Architecture Exploiting Per-victim-row Counting
Jumin Kim, Seungmin Baek, Hwayong Nam +3
As DRAM scaling exacerbates RowHammer, DDR5 introduces per-row activation counting (PRAC) to track aggressor activity. However, PRAC indiscriminately increments counters on every a…
cs.AR2025
A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
Haneul Park, Jiaqi Lou, Sangjin Lee +5
In modern server CPUs, the Last-Level Cache (LLC) serves not only as a victim cache for higher-level private caches but also as a buffer for low-latency DMA transfers between CPU c…
cs.AR2023★ 22 cited
A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors
Reese Kuper, Ipoom Jeong, Yifan Yuan +4
As semiconductor power density is no longer constant with the technology process scaling down, modern CPUs are integrating capable data accelerators on chip, aiming to improve perf…