19 citations · 25 across the 11 of their papers we have counts for
12 papers
BOOST: Concurrent Access to Host Memory and HBM to Accelerate LLM Inference
Anish Saxena, Jae Hyung Ju, Hritvik Taneja +4
GPU memory bandwidth and capacity limit throughput in large language model (LLM) inference. The GPU memory system consists of a primary tier of high-bandwidth memory (HBM) and a se…
Loaded Dice: Solving the Non-Selection Problem for Scalable Probabilistic RowHammer Defense
Jeonghyun Woo, Junsu Kim, Aamer Jaleel +1
DRAM scaling has exacerbated the RowHammer vulnerability. To counter this, JEDEC recently introduced Per Row Activation Counting (PRAC) with the Alert Back-Off protocol as an optio…
Utility-Driven Speculative Decoding for Mixture-of-Experts
Anish Saxena, Po-An Tsai, Hritvik Taneja +2
GPU memory bandwidth is the main bottleneck for low-latency Large Language Model (LLM) inference. Speculative decoding leverages idle GPU compute by using a lightweight drafter to…
GPUArmor: A Hardware-Software Co-design for Efficient and Scalable Memory Safety on GPUs
Mohamed Tarek Ibn Ziad, Sana Damani, Mark Stephenson +2
Memory safety errors continue to pose a significant threat to current computing systems, and graphics processing units (GPUs) are no exception. A prominent class of memory safety a…
QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues
Jeonghyun Woo, Chris S. Lin, Prashant J. Nair +2
JEDEC has introduced the Per Row Activation Counting (PRAC) framework for DDR5 and future DRAMs to enable precise counting of DRAM row activations. PRAC enables a holistic mitigati…
Teaching an Old Dog New Tricks: Verifiable FHE Using Commodity Hardware
Jules Drean, Fisher Jepsen, Edward Suh +3
We present Argos, a simple approach for adding verifiability to fully homomorphic encryption (FHE) schemes using trusted hardware. Traditional approaches to verifiable FHE require…
MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker
Moinuddin Qureshi, Salman Qazi, Aamer Jaleel
This paper investigates secure low-cost in-DRAM trackers for mitigating Rowhammer (RH). In-DRAM solutions have the advantage that they can solve the RH problem within the DRAM chip…
ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation
Moinuddin Qureshi, Anish Saxena, Aamer Jaleel
DRAM cells are susceptible to Data-Disturbance Errors (DDE), which can be exploited by an attacker to compromise system security. Rowhammer is a well-known DDE vulnerability that o…
Improving Multi-Instance GPU Efficiency via Sub-Entry Sharing TLB Design
Bingyao Li, Yueqi Wang, Tianyu Wang +4
NVIDIA's Multi-Instance GPU (MIG) technology enables partitioning GPU computing power and memory into separate hardware instances, providing complete isolation including compute re…
Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation
Aamer Jaleel, Stephen W. Keckler, Gururaj Saileshwar
This paper focuses on mitigating DRAM Rowhammer attacks. In recent years, solutions like TRR have been deployed in DDR4 DRAM to track aggressor rows and then issue a mitigative act…
HAPPY: Hybrid Address-based Page Policy in DRAMs
Mohsen Ghasempour, Aamer Jaleel, Jim Garside +1
Memory controllers have used static page closure policies to decide whether a row should be left open, open-page policy, or closed immediately, close-page policy, after the row has…
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs
Mohsen Ghasempour, Jim Garside, Aamer Jaleel +1
The initial location of data in DRAMs is determined and controlled by the 'address-mapping' and even modern memory controllers use a fixed and run-time-agnostic address mapping. On…