3 papers
cs.AR2026
Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure
Chengjia Liu, Priyadarsi Mishra, David Kebo Houngninou +3
Last-mile functional coverage closure for modern chip designs remains costly because a mature UVM environment exposes many controls while direct hits on the remaining bins are spar…
cs.SE2025
BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis
Surya Jasper, Minh Luu, Evan Pan +4
Hardware complexity continues to strain verification resources, motivating the adoption of machine learning (ML) methods to improve debug efficiency. However, ML-assisted debugging…
cs.AR2025
Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization
Fenghua Wu, Evan Pan, Rahul Kande +5
SystemVerilog Assertions (SVAs) play a critical role in detecting and debugging functional bugs in digital chip design. However, generating SVAs has traditionally been a manual, la…