3 papers
cs.AR2026
ConnChecker: Automated Root-Cause Analysis for Formal Connectivity Check via Graph
Do Ngoc Tiep, Nguyen Linh Anh, Luu Danh Minh
Formal connectivity checking offers scalable verification of signal paths in complex SoC designs, but debugging counterexamples remains a manual and time-consuming process. ConnChe…
cs.SE2025
BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis
Surya Jasper, Minh Luu, Evan Pan +4
Hardware complexity continues to strain verification resources, motivating the adoption of machine learning (ML) methods to improve debug efficiency. However, ML-assisted debugging…
cs.LG2025
VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration
Minh Luu, Surya Jasper, Khoi Le +4
Failure triage in design functional verification is critical but time-intensive, relying on manual specification reviews, log inspections, and waveform analyses. While machine lear…