4 papers
Assertain: Automated Security Assertion Generation Using Large Language Models
Shams Tarek, Dipayan Saha, Khan Thamid Hasan +3
The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property…
AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study
Khan Thamid Hasan, Md Ajoad Hasan, Nashmin Alam +3
As hardware systems grow in complexity, security verification must keep up with them. Recently, artificial intelligence (AI) and large language models (LLMs) have started to play a…
LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification
Md Ajoad Hasan, Dipayan Saha, Khan Thamid Hasan +5
The growing complexity of modern system-on-chip (SoC) and IP designs is making security assurance difficult day by day. One of the fundamental steps in the pre-silicon security ver…
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Dipayan Saha, Shams Tarek, Hasan Al Shaikh +8
Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenge…