4 papers · 1 filter
Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
En-Ming Huang, Yu-Hung Kao, Ren-Hao Deng +10
Automated testbench generation has become a critical bottleneck in large language model (LLM)-driven Register Transfer Level (RTL) workflows, where large numbers of candidate desig…
Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
Mu-Chi Chen, Po-Hsuan Huang, Yu-Hung Kao +6
Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches fo…
ParaQAOA: Efficient Parallel Divide-and-Conquer QAOA for Large-Scale Max-Cut Problems Beyond 10,000 Vertices
Po-Hsuan Huang, Xie-Ru Li, Chi Chuang +2
Quantum Approximate Optimization Algorithm (QAOA) has emerged as a promising solution for combinatorial optimization problems using a hybrid quantum-classical framework. Among comb…
SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
Mu-Chi Chen, Yu-Hung Kao, Po-Hsuan Huang +10
Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctne…