7 citations · 10 across the 7 of their papers we have counts for
7 papers
EDATracer: An Agentic Framework for Large-Scale EDA Artifact Analysis
Phat Tieu, Sayanti Jana, Matthew DeLorenzo +5
Modern chip design relies on electronic design automation (EDA) tools that generate large, heterogeneous artifacts, including source files, scripts, logs, netlists, and reports. An…
GUIDE: GenAI Units In Digital Design Education
Weihua Xiao, Jason Blocklove, Matthew DeLorenzo +6
GenAI Units In Digital Design Education (GUIDE) is an open courseware repository with runnable Google Colab labs and other materials. We describe the repository's architecture and…
Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs
Sam Bush, Matthew DeLorenzo, Phat Tieu +1
Limitations in Large Language Model (LLM) capabilities for hardware design tasks, such as generating functional Verilog codes, have motivated various fine-tuning optimizations util…
Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design
Matthew DeLorenzo, Kevin Tieu, Prithwish Jana +4
Large language models (LLMs) have achieved impressive proficiency on logic and programming tasks, often rivaling expert-level performance. However, generating functionally correct…
LLMPirate: LLMs for Black-box Hardware IP Piracy
Vasudev Gohil, Matthew DeLorenzo, Veera Vishwa Achuta Sai Venkat Nallam +2
The rapid advancement of large language models (LLMs) has enabled the ability to effectively analyze and generate code nearly instantaneously, resulting in their widespread adoptio…
CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation
Matthew DeLorenzo, Vasudev Gohil, Jeyavijayan Rajendran
Large Language Models (LLMs) have proved effective and efficient in generating code, leading to their utilization within the hardware design process. Prior works evaluating LLMs' a…
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Matthew DeLorenzo, Animesh Basak Chowdhury, Vasudev Gohil +4
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) effici…