3 citations · 3 across the 3 of their papers we have counts for
5 papers
CACHEFORGE: LLM-Guided End-to-End Generative Cache Replacement Policy for Performance and Hardware Efficiency
Kaushal Mhapsekar, Bita Aslrousta, Brijesh Kumar Bhayana +5
Modern cache replacement designs saturate because they operate within fixed representational structures, hand-crafted and heuristic based feature-engineered predictors, or offline…
CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies
Bita Aslrousta, Kaushal Mhapsekar, Darsh Asher +3
The latency, power, and area costs of LLC replacement remain poorly explored not because simulators cannot be instrumented--event counters feeding a power model are routine--but be…
CacheMind: From Miss Rates to Why -- Natural-Language, Trace-Grounded Reasoning for Cache Replacement
Kaushal Mhapsekar, Azam Ghanbari, Bita Aslrousta +1
Cache replacement remains a challenging problem in CPU microarchitecture, often addressed using hand-crafted heuristics, limiting cache performance. Cache data analysis requires pa…
GATEBLEED: Exploiting On-Core Accelerator Power Gating for High Performance & Stealthy Attacks on AI
Joshua Kalyanapu, Farshad Dizani, Darsh Asher +4
As power consumption from AI training and inference continues to increase, AI accelerators are being integrated directly into the CPU. Intel's Advanced Matrix Extensions (AMX) is o…
THOR: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
Farshad Dizani, Azam Ghanbari, Joshua Kalyanapu +2
The rise of on-chip accelerators signifies a major shift in computing, driven by the growing demands of artificial intelligence (AI) and specialized applications. These accelerator…