6 papers
ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards
Prashanth Vijayaraghavan, Charles Mackin, Luyao Shi +6
Large language models (LLMs) have shown promise in code summarization, yet their effectiveness for Hardware Description Languages (HDLs) like VHDL and Verilog remains underexplored…
StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis
Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +2
Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon reasoning, multi-step dependencies, and strict correctness constraints in Veri…
SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization
Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +5
Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax,…
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
Prashanth Vijayaraghavan, Apoorva Nitsure, Charles Mackin +9
Large Language Models (LLMs) have become widely used across diverse NLP tasks and domains, demonstrating their adaptability and effectiveness. In the realm of Electronic Design Aut…
Improving LLM-Powered EDA Assistants with RAFT
Luyao Shi, Michael Kazda, Charles Schmitter +1
Electronic design engineers often struggle to efficiently access relevant information for tasks like design verification and technology development. While large language models (LL…
AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation
Prashanth Vijayaraghavan, Luyao Shi, Ehsan Degan +2
Analog circuit topology synthesis is integral to Electronic Design Automation (EDA), enabling the automated creation of circuit structures tailored to specific design requirements.…