4 papers · 1 filter
ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards
Prashanth Vijayaraghavan, Charles Mackin, Luyao Shi +6
Large language models (LLMs) have shown promise in code summarization, yet their effectiveness for Hardware Description Languages (HDLs) like VHDL and Verilog remains underexplored…
SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization
Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +5
Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax,…
CODMAS: A Dialectic Multi-Agent Collaborative Framework for Structured RTL Optimization
Che-Ming Chang, Prashanth Vijayaraghavan, Ashutosh Jadhav +4
Optimizing Register Transfer Level (RTL) code is a critical step in Electronic Design Automation (EDA) for improving power, performance, and area (PPA). We present CODMAS (Collabor…
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
Prashanth Vijayaraghavan, Apoorva Nitsure, Charles Mackin +9
Large Language Models (LLMs) have become widely used across diverse NLP tasks and domains, demonstrating their adaptability and effectiveness. In the realm of Electronic Design Aut…