activity
20242026
most citedChain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization

7 citations · 9 across the 9 of their papers we have counts for

collaborators

10 papers

cs.CL2026

ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards

Prashanth Vijayaraghavan, Charles Mackin, Luyao Shi +6

Large language models (LLMs) have shown promise in code summarization, yet their effectiveness for Hardware Description Languages (HDLs) like VHDL and Verilog remains underexplored…

cs.AI2026

StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis

Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +2

Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon reasoning, multi-step dependencies, and strict correctness constraints in Veri…

cs.CL2026

SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization

Prashanth Vijayaraghavan, Apoorva Nitsure, Luyao Shi +5

Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax,…

cs.CL2025★ 7 cited

Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization

Prashanth Vijayaraghavan, Apoorva Nitsure, Charles Mackin +9

Large Language Models (LLMs) have become widely used across diverse NLP tasks and domains, demonstrating their adaptability and effectiveness. In the realm of Electronic Design Aut…

cs.CL2025

Improving LLM-Powered EDA Assistants with RAFT

Luyao Shi, Michael Kazda, Charles Schmitter +1

Electronic design engineers often struggle to efficiently access relevant information for tasks like design verification and technology development. While large language models (LL…

cs.CL2025

AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation

Prashanth Vijayaraghavan, Luyao Shi, Ehsan Degan +2

Analog circuit topology synthesis is integral to Electronic Design Automation (EDA), enabling the automated creation of circuit structures tailored to specific design requirements.…

cs.CL2024

Self-Regulated Data-Free Knowledge Amalgamation for Text Classification

Prashanth Vijayaraghavan, Hongzhi Wang, Luyao Shi +3

Recently, there has been a growing availability of pre-trained text models on various model repositories. These models greatly reduce the cost of training new models from scratch a…

cs.LG2024

CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesis

Prashanth Vijayaraghavan, Luyao Shi, Ehsan Degan +1

Circuit topology generation plays a crucial role in the design of electronic circuits, influencing the fundamental functionality of the circuit. In this paper, we introduce CIRCUIT…

cs.SE2024★ 1 cited

VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generation

Prashanth Vijayaraghavan, Luyao Shi, Stefano Ambrogio +4

With the unprecedented advancements in Large Language Models (LLMs), their application domains have expanded to include code generation tasks across various programming languages.…

cs.CL2024★ 1 cited

Ask-EDA: A Design Assistant Empowered by LLM, Hybrid RAG and Abbreviation De-hallucination

Luyao Shi, Michael Kazda, Bradley Sears +2

Electronic design engineers are challenged to find relevant information efficiently for a myriad of tasks within design construction, verification and technology development. Large…