Showing cs.ARShow all
3 papers · 1 filter
cs.AR2026
AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting
Yiting Wang, Chenhui Deng, Chia-Tung Ho +6
Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, yet current FGCG optimization flows remain largely manual. Recent LLM-based RTL op…
cs.AR2025
MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization
Yiting Wang, Wanghao Ye, Yexiao He +3
This paper presents MCP4EDA, the first Model Context Protocol server that enables Large Language Models (LLMs) to control and optimize the complete open-source RTL-to-GDSII design…
cs.AR2025
SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning
Yiting Wang, Wanghao Ye, Ping Guo +11
Optimizing Register Transfer Level (RTL) code is crucial for improving the power, performance, and area (PPA) of digital circuits in the early stages of synthesis. Manual rewriting…