1 citations · 1 across the 6 of their papers we have counts for
7 papers
Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
Jingyi Zhou, Zhengyuan Shi, Jiaying Zhu +2
Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the…
Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
Jiaying Zhu, Zhengyuan Shi, Mengxia Tao +3
Logic Equivalence Checking (LEC), a fundamental hardware verification task, is often bottlenecked by synthesis-induced structural perturbations and XOR-dense regions that degrade S…
EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
Jiaying Zhu, Baoqi Zhang, Mengxia Tao +4
Ensuring functional consistency between high-level algorithmic models and low-level hardware implementations is a critical challenge, particularly as modern design flows increasing…
TRACE: Learning to Compute on Circuit Graphs
Ziyang Zheng, Jiaying Zhu, Jingyi Zhou +1
Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning. Yet, the dominant paradigm is ar…
Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities
Jiaying Zhu, Ziyang Zheng, Zhengyuan Shi +2
Circuit Satisfiability (CSAT) plays a pivotal role in Electronic Design Automation. The standard workflow for solving CSAT problems converts circuits into Conjunctive Normal Form (…
ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA
Zhengyuan Shi, Zeju Li, Chengyu Ma +19
We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RT…
Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
Zhengyuan Shi, Tiebing Tang, Jiaying Zhu +5
The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and verification. However, exis…