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cs.AR2025
ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis
Suresh Purini, Siddhant Garg, Mudit Gaur +3
Modern SoC datapaths include deeply pipelined, domain-specific accelerators, but their RTL implementation and verification are still mostly done by hand. While large language model…
cs.AR2024
AiEDA: Agentic AI Design Framework for Digital ASIC System Design
Aditya Patra, Saroj Rout, Arun Ravindran
The paper addresses advancements in Generative Artificial Intelligence (GenAI) and digital chip design, highlighting the integration of Large Language Models (LLMs) in automating h…