30 citations · 31 across the 8 of their papers we have counts for
8 papers
Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
Ruiyang Ma, Daikang Kuang, Ziqian Liu +3
Debugging hardware designs requires significant manual effort during hardware development. After engineers identify a bug-triggering test case in simulation-based hardware verifica…
Bridging the Gap between Hardware Fuzzing and Industrial Verification
Ruiyang Ma, Tianhao Wei, Jiaxi Zhang +3
As hardware design complexity increases, hardware fuzzing emerges as a promising tool for automating the verification process. However, a significant gap still exists before it can…
VerilogReader: LLM-Aided Hardware Test Generation
Ruiyang Ma, Yuxin Yang, Ziqian Liu +4
Test generation has been a critical and labor-intensive process in hardware design verification. Recently, the emergence of Large Language Model (LLM) with their advanced understan…
MEC: An Open-source Fine-grained Mapping Equivalence Checking Tool for FPGA
Liwei Ni, Zonglin Yang, Jiaxi Zhang +6
Technology mapping is an essential step in EDA flow. However, the function of the circuit may be changed after technology mapping, and equivalence checking (EC) based verification…
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning
Liwei Ni, Zonglin Yang, Jiaxi Zhang +4
Rewriting is a common procedure in logic synthesis aimed at improving the performance, power, and area (PPA) of circuits. The traditional reconvergence-driven And-Inverter Graph (A…
Fast Exact NPN Classification with Influence-aided Canonical Form
Yonghe Zhang, Liwei Ni, Jiaxi Zhang +3
NPN classification has many applications in the synthesis and verification of digital circuits. The canonical-form-based method is the most common approach, designing a canonical f…
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions
Jiaxi Zhang, Shenggen Zheng, Liwei Ni +2
NPN classification is an essential problem in the design and verification of digital circuits. Most existing works explored variable symmetries and cofactor signatures to develop t…
Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning
Jiaxi Zhang, Liwei Ni, Shenggen Zheng +4
Boolean matching is significant to digital integrated circuits design. An exhaustive method for Boolean matching is computationally expensive even for functions with only a few var…