most citedSecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip

2 citations · 2 across the 2 of their papers we have counts for

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cs.CR2025

VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog

Xiang Long, Yingjie Xia, Xiyuan Chen +1

Timely detection of hardware vulnerabilities during the early design stage is critical for reducing remediation costs. Existing early detection techniques often require specialized…

cs.CR2025★ 2 cited

SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip

Ziteng Hu, Yingjie Xia, Xiyuan Chen +1

Finite State Machines (FSMs) play a critical role in implementing control logic for Systems-on-Chip (SoC). Traditionally, FSMs are implemented by hardware engineers through Verilog…