most citedSecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip

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cs.AR2025

ViTAD: Timing Violation-Aware Debugging of RTL Code using Large Language Models

Wenhao Lv, Yingjie Xia, Xiyuan Chen +1

In modern Very Large Scale Integrated (VLSI) circuit design flow, the Register-Transfer Level (RTL) stage presents a critical opportunity for timing optimization. Addressing timing…