2 citations · 2 across the 3 of their papers we have counts for
4 papers
When LLMs Over-Answer: Measuring and Mitigating Quality Issues in LLM-Based Hardware Description Language Question Answering
Ziteng Hu, Jiachi Chen, Wenhao Lv +2
The rapid advancement of large language models (LLMs) has led practitioners to increasingly rely on them for answering questions about hardware description languages (HDLs). Becaus…
VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog
Xiang Long, Yingjie Xia, Xiyuan Chen +1
Timely detection of hardware vulnerabilities during the early design stage is critical for reducing remediation costs. Existing early detection techniques often require specialized…
SecFSM: Knowledge Graph-Guided Verilog Code Generation for Secure Finite State Machines in Systems-on-Chip
Ziteng Hu, Yingjie Xia, Xiyuan Chen +1
Finite State Machines (FSMs) play a critical role in implementing control logic for Systems-on-Chip (SoC). Traditionally, FSMs are implemented by hardware engineers through Verilog…
ViTAD: Timing Violation-Aware Debugging of RTL Code using Large Language Models
Wenhao Lv, Yingjie Xia, Xiyuan Chen +1
In modern Very Large Scale Integrated (VLSI) circuit design flow, the Register-Transfer Level (RTL) stage presents a critical opportunity for timing optimization. Addressing timing…