13 papers
FABO: Agent-Guided Discovery of Joint Breakpoint Optimization for Timing-Driven Routing Trees
Shang Liu, Wenji Fang, Jing Wang +3
The topology of a routing tree determines how a multi-pin net branches and shares physical wire, directly affecting wirelength, congestion, capacitance, and delay. We study a centr…
ComPart: Community-Guided Post-Coarsening for High-Quality Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Yuchao Wu +3
Hypergraph partitioning is a critical step in the design of complex embedded systems, essential for optimizing task mapping on heterogeneous MPSoCs and enabling multi-FPGA prototyp…
IMPart: Integration of Memetic Operations into Multi-Level Framework for Large-k-Way Hypergraph Partitioning
Yugao Zhu, Zhicheng Guo, Shang Liu +3
The problem of k-way hypergraph partitioning is fundamental with significant applications in various fields, including VLSI design and scientific computing. State-of-the-art hyperg…
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
Jing Wang, Shang Liu, Wenji Fang +3
LLM-based RTL generation and reasoning is a promising direction for hardware design automation. High-quality benchmarks are critical infrastructure for tracking progress in this di…
AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications
Yuchao Wu, Wenji Fang, Jing Wang +3
Assertion-based verification (ABV) is a cornerstone of modern hardware design, yet manually translating design intent into formal SystemVerilog Assertions (SVAs) remains labor-inte…
RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
Jing Wang, Shang Liu, Hangan Zhou +1
This paper introduces RTL-BenchMT, an agentic framework for dynamically maintaining RTL generation benchmarks. Large Language Models (LLMs) assisted automated RTL generation is one…
AnalogRetriever: Learning Cross-Modal Representations for Analog Circuit Retrieval
Yihan Wang, Lei Li, Yao Lai +2
Analog circuit design relies heavily on reusing existing intellectual property (IP), yet searching across heterogeneous representations such as SPICE netlists, schematics, and func…
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
Shang Liu, Jing Wang, Wenji Fang +1
In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain.…
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
Wenkai Li, Yao Lu, Wenji Fang +3
Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, tradi…
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions
Jing Wang, Shang Liu, Yao Lu +1
High-level synthesis (HLS) accelerates hardware design by enabling the automatic translation of high-level descriptions into efficient hardware implementations. However, debugging…
EarthCrafter: Scalable 3D Earth Generation via Dual-Sparse Latent Diffusion
Shang Liu, Chenjie Cao, Chaohui Yu +3
Despite the remarkable developments achieved by recent 3D generation works, scaling these methods to geographic extents, such as modeling thousands of square kilometers of Earth's…
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
Wenji Fang, Shang Liu, Jing Wang +1
The rapid advancements of AI rely on the support of ICs. However, the growing complexity of digital ICs makes the traditional IC design process costly and time-consuming. In recent…
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
Wenji Fang, Jing Wang, Yao Lu +4
Artificial intelligence (AI)-driven electronic design automation (EDA) techniques have been extensively explored for VLSI circuit design applications. Most recently, foundation AI…