9 papers · 1 filter
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
Raghu Vamshi Hemadri, Jitendra Bhandari, Andre Nakkab +5
Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a…
PrefixLLM: LLM-aided Prefix Circuit Design
Weihua Xiao, Venkata Sai Charan Putrevu, Raghu Vamshi Hemadri +2
Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with…
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
Luca Collini, Siddharth Garg, Ramesh Karri
High-Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This paper investigates Large Language Models (LLMs…
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
Jitendra Bhandari, Vineet Bhat, Yuheng He +3
Masala-CHAI is a fully automated framework leveraging large language models (LLMs) to generate Simulation Programs with Integrated Circuit Emphasis (SPICE) netlists. It addresses a…
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan +3
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-pron…
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
Andre Nakkab, Sai Qian Zhang, Ramesh Karri +1
Large Language Models (LLMs) are effective in computer hardware synthesis via hardware description language (HDL) generation. However, LLM-assisted approaches for HDL generation st…