4 papers
A Generic Modulo- RNS Multiplier Based on Twit Representation
Saeid Gorgin, Amirhossein Sadr, Behzad Salami +1
Modular multiplication is a fundamental arithmetic primitive in Residue Number Systems (RNS) and is often the dominant source of delay, area, and energy consumption in RNS datapath…
REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton
Noelia Oliete-EscuÃn, Arnau Bigas, NarcÃs Rodas +26
Chip industry continues advancing and expanding modern computing systems, resulting in more complex multi-core processors. Conversely, academic projects face scalability challenges…
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
EMiX: Emulating Beyond Single-FPGA Limits
Alexander Kropotov, Miquel Moreto, Behzad Salami
FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale multi-core systems increasingly exceed the hardware resource capacity of a…