3 papers
cs.AR2026
VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
Yan Tan, Tong Liu, Xiangchen Meng +1
Large Language Models (LLMs) have recently achieved strong performance in software code generation. However, applying them to hardware description languages (HDLs), such as Verilog…
cs.PL2026
AutoVeriFix+: High-Correctness RTL Generation via Trace-Aware Causal Fix and Semantic Redundancy Pruning
Yan Tan, Xiangchen Meng, Zijun Jiang +1
Large language models (LLMs) have demonstrated impressive capabilities in generating software code for high-level programming languages such as Python and C++. However, their appli…
cs.AR2025
AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code
Yan Tan, Xiangchen Meng, Zijun Jiang +1
Large language models (LLMs) have demonstrated impressive capabilities in generating software code for high-level programming languages such as Python and C++. However, their appli…