3 papers
cond-mat.mes-hall2026
Unveiling the Scaling Potential of Drain Merge through Active (DMtA) in CFETs: Breaking the Super-Via Bottlenecks and Unlocking New PPA Boosters
Jingru Jiang, Haoran Lu, Kairong Guo +11
Drain merge (DM), a super via vertically connecting the common S/D terminals of stacked n/pFETs in Complementary FETs (CFETs), blocks further parasitic optimization and cell scalin…
cs.LG2026
FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
Haoyi Zhang, Kairong Guo, Bojie Zhang +2
Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulat…
cs.AR2025
Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization
Yi Ren, Baokang Peng, Chenhao Xue +6
With the diminishing return from Moore's Law, system-technology co-optimization (STCO) has emerged as a promising approach to sustain the scaling trends in the VLSI industry. By br…