3 citations · 7 across the 6 of their papers we have counts for
6 papers
Testing and Fault Tolerance Techniques for CNT-Based FPGAs
Siyuan Lu, Kangwei Xu, Peng Xie +2
As the semiconductor manufacturing process technology node shrinks into the nanometer-scale, the CMOS-based Field Programmable Gate Arrays (FPGAs) face big challenges in scalabilit…
Large Language Models (LLMs) for Electronic Design Automation (EDA)
Kangwei Xu, Denis Schwachhofer, Jason Blocklove +10
With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufacturing workflow. This workflow involve…
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis
Kangwei Xu, Bing Li, Grace Li Zhang +1
In high-level synthesis (HLS), C/C++ programs with synthesis directives are used to generate circuits for FPGA implementations. However, hardware-specific and platform-dependent ch…
LLM-Aided Efficient Hardware Design Automation
Kangwei Xu, Ruidi Qiu, Zhuorui Zhao +3
With the rapidly increasing complexity of modern chips, hardware engineers are required to invest more effort in tasks such as circuit design, verification, and physical implementa…
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models
Kangwei Xu, Grace Li Zhang, Xunzhao Yin +3
In High-Level Synthesis (HLS), converting a regular C/C++ program into its HLS-compatible counterpart (HLS-C) still requires tremendous manual effort. Various program scripts have…
Logic Design of Neural Networks for High-Throughput and Low-Power Applications
Kangwei Xu, Grace Li Zhang, Ulf Schlichtmann +1
Neural networks (NNs) have been successfully deployed in various fields. In NNs, a large number of multiplyaccumulate (MAC) operations need to be performed. Most existing digital h…