2 citations · 2 across the 2 of their papers we have counts for
2 papers
physics.app-ph2026
Are gate-all-around 2D CFETs the optimal architecture for the A2 node and beyond?
Fengben Xi, Gautam Gaddemane, Anshul Gupta +15
As logic scaling enters the angstrom era, vertically stacked complementary field-effect transistors (CFETs) based on atomically thin two-dimensional (2D) semiconductors offer a pot…
cs.ET2025★ 2 cited
SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study
Yang Xiang, Fernando García-Redondo, Arvind Sharma +9
This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-…