most citedOpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

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cs.CL2026★ 1 cited

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

Jinghua Wang, Lily Jiaxin Wan, Sanjana Pingali +6

OpenRTLSet introduces the largest fully open-source dataset for hardware design, offering over 131,000 diverse Verilog code samples to the research community and industry. Our data…