3 papers
cs.CL2026
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
Jinghua Wang, Lily Jiaxin Wan, Sanjana Pingali +6
OpenRTLSet introduces the largest fully open-source dataset for hardware design, offering over 131,000 diverse Verilog code samples to the research community and industry. Our data…
cs.AR2026
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
Lily Jiaxin Wan, Chia-Tung Ho, Yunsheng Bai +4
The remarkable reasoning and code generation capabilities of large language models (LLMs) have recently motivated increasing interest in automating formal verification (FV), a proc…
cs.AI2025
SchemaCoder: Automatic Log Schema Extraction Coder with Residual Q-Tree Boosting
Lily Jiaxin Wan, Chia-Tung Ho, Rongjian Liang +3
Log schema extraction is the process of deriving human-readable templates from massive volumes of log data, which is essential yet notoriously labor-intensive. Recent studies have…