6 citations · 11 across the 6 of their papers we have counts for
6 papers
Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors
Alessandro Ottaviano, Andrino Meli, Paul Scheffler +5
Managing energy and thermal profiles is critical for many-core HPC processors with hundreds of application-class processing elements (PEs). Advanced model predictive control (MPC)…
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Zexin Fu, Riccardo Tedeschi, Gianmarco Ottavi +4
Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO…
CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
Riccardo Tedeschi, Gianmarco Ottavi, Côme Allart +11
Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on t…
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti +20
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ens…
Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor
Riccardo Tedeschi, Luca Valente, Gianmarco Ottavi +6
Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardwar…
TOP: Towards Open & Predictable Heterogeneous SoCs
Luca Valente, Francesco Restuccia, Davide Rossi +2
Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial aut…