14 citations · 35 across the 14 of their papers we have counts for
14 papers
CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems
Enrico Zelioli, Christopher Reinwardt, Nils Wistoff +4
This work presents CVA6-RT, a real-time micro-architectural extension of the CVA6 core to bound worst-case latency and reduce task's timing execution variability. CVA6-RT implement…
Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors
Alessandro Ottaviano, Andrino Meli, Paul Scheffler +5
Managing energy and thermal profiles is critical for many-core HPC processors with hundreds of application-class processing elements (PEs). Advanced model predictive control (MPC)…
CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
Christopher Reinwardt, Robert Balas, Alessandro Ottaviano +2
The increasing complexity of autonomous systems has driven a shift to integrated heterogeneous SoCs with real-time and safety demands. Ensuring deterministic WCETs and low-latency…
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti +20
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ens…
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
Thomas Benz, Alessandro Ottaviano, Chaoqun Liang +6
The automotive industry is transitioning from federated, homogeneous, interconnected devices to integrated, heterogeneous, mixed-criticality systems (MCS). This leads to challenges…
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems
Enrico Zelioli, Alessandro Ottaviano, Robert Balas +3
The widespread diffusion of compute-intensive edge-AI workloads and the stringent demands of modern autonomous systems require advanced heterogeneous embedded architectures. Such a…
ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
Alessandro Ottaviano, Robert Balas, Tim Fischer +3
The growing complexity of real-time control algorithms with increasing performance demands, along with the shift to 2.5D technology, drive the need for scalable controllers to mana…
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz +4
In the last decade, we have witnessed exponential growth in the complexity of control systems for safety-critical applications (automotive, robots, industrial automation) and their…
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs
Thomas Benz, Alessandro Ottaviano, Robert Balas +4
The increasing demand for heterogeneous functionality in the automotive industry and the evolution of chip manufacturing processes have led to the transition from federated to inte…
Well-being in isolation: Exploring artistic immersive virtual environments in a simulated lunar habitat to alleviate asthenia symptoms
Grzegorz Pochwatko, Wieslaw Kopec, Justyna Swidrak +14
Revived interest in lunar and planetary exploration is heralding a new era for human spaceflight, characterized by frequent strain on astronaut's mental well-being, which stems fro…
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers
Robert Balas, Alessandro Ottaviano, Luca Benini
Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, an…
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
Alessandro Ottaviano, Robert Balas, Philippe Sauter +2
A key challenge for ultra-low-power (ULP) devices is handling peripheral linking, where the main central processing unit (CPU) periodically mediates the interaction among multiple…
Towards a RISC-V Open Platform for Next-generation Automotive ECUs
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano +5
The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity po…
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
Alessandro Ottaviano, Robert Balas, Giovanni Bambini +5
High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex and high-bandwidth closed-loop power and thermal control strategies. To…