5 papers
A FeFET Voltage-to-Time Converter with Offset Trim by Programmed Multilevel State in 28-nm CMOS
Jeries Mattar, Hanaa Eqeiq, Stefan Dünkel +4
The offset and gain of voltage-to-time converters (VTCs) in time-domain circuits vary with process, supply, and temperature. This work presents a VTC whose nonvolatile input-referr…
A 185 TOPS/W/mm2 Bayesian Inference Engine with 640 aJ Write-Free FeFET GRNG for Uncertainty-Aware Aerial Search and Rescue
Zephan M. Enciso, Xuezhong Niu, Xingtian Wang +9
Aerial search and rescue missions require fast and reliable victim detection under uncertain and rapidly changing environments. Deterministic deep learning models can produce overc…
Symbol Detection in a MIMO Wireless Communication System Using a FeFET-coupled CMOS Ring Oscillator Array
Harsh Kumar Jadia, Abhinaba Ghosh, Md Hanif Ali +11
Symbol decoding in multiple-input multiple-output (MIMO) wireless communication systems requires the deployment of fast, energy-efficient computing hardware deployable at the edge.…
A Reconfigurable Time-Domain In-Memory Computing Macro using FeFET-Based CAM with Multilevel Delay Calibration in 28 nm CMOS
Jeries Mattar, Mor M. Dahan, Stefan Dunkel +5
Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than…
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate
Zijian Zhao, Sola Woo, Khandker Akif Aabrar +22
In this work, we propose a dual-port cell design to address the pass disturb in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. W…