3 papers
cs.AR2026
BRIM: Workload-Balanced Dual-Sided Bit-Serial Sparse Inference Accelerator
Varun Manjunath, Ruokai Yin, Donghyun Lee +2
Bit-serial accelerators exploit bit-level sparsity to reduce DNN inference cost, but existing designs exploit sparsity on only one operand, bounding the speedup. Extending sparsity…
cs.NE2025
NeuroFlex: Column-Exact ANN-SNN Co-Execution Accelerator with Cost-Guided Scheduling
Varun Manjunath, Pranav Ramesh, Gopalakrishnan Srinivasan
NeuroFlex is a column-level accelerator that co-executes artificial and spiking neural networks to minimize energy-delay product on sparse edge workloads with competitive accuracy.…
cs.AR2024
Chiplets on Wheels: Review Paper on Holistic Chiplet Solutions for Autonomous Vehicles
Swathi Narashiman, Venkat A, Divyaratna Joshi +7
On the advent of the slow death of Moore's law, the silicon industry is moving towards a new era of chiplets. The automotive industry is experiencing a profound transformation towa…