3 citations · 7 across the 6 of their papers we have counts for
6 papers
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
Jialin Sun, Yuchen Hu, Dean You +6
Functional verification is a critical bottleneck in integrated circuit development, with CPU verification being especially time-intensive and labour-consuming. Industrial practice…
Re-thinking Memory-Bound Limitations in CGRAs
Xiangfeng Liu, Zhe Jiang, Anzhen Zhu +4
Coarse-Grained Reconfigurable Arrays (CGRAs) are specialized accelerators commonly employed to boost performance in workloads with iterative structures. Existing research typically…
ARSP: Automated Repair of Verilog Designs via Semantic Partitioning
Bingkun Yao, Ning Wang, Xiangfeng Liu +5
Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this e…
UVLLM: An Automated Universal RTL Verification Framework using LLMs
Yuchen Hu, Junhao Ye, Ke Xu +11
Verifying hardware designs in embedded systems is crucial but often labor-intensive and time-consuming. While existing solutions have improved automation, they frequently rely on u…
Estimating Treatment Effects under Algorithmic Interference: A Structured Neural Networks Approach
Ruohan Zhan, Shichao Han, Yuchen Hu +1
Online user-generated content platforms allocate billions of dollars of promotional traffic through algorithms in two-sided marketplaces. To evaluate updates to these algorithms, p…
MEIC: Re-thinking RTL Debug Automation using LLMs
Ke Xu, Jialin Sun, Yuchen Hu +4
The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts.…