2 citations · 5 across the 7 of their papers we have counts for
4 papers · 1 filter
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
Jialin Sun, Yuchen Hu, Dean You +6
Functional verification is a critical bottleneck in integrated circuit development, with CPU verification being especially time-intensive and labour-consuming. Industrial practice…
Exploiting the Uncertainty of the Longest Paths: Response Time Analysis for Probabilistic DAG Tasks
Yiyang Gao, Shuai Zhao, Boyang Li +4
Parallel real-time systems (e.g., autonomous driving systems) often contain functionalities with complex dependencies and execution uncertainties, leading to significant timing var…
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
Junhao Ye, Yuchen Hu, Ke Xu +8
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology…
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Jie Zhou, Youshu Ji, Ning Wang +7
SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours…