2 citations · 10 across the 13 of their papers we have counts for
8 papers · 1 filter
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
Junhao Ye, Dingrong Pan, Hanyuan Liu +7
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves r…
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
Jialin Sun, Yuchen Hu, Dean You +6
Functional verification is a critical bottleneck in integrated circuit development, with CPU verification being especially time-intensive and labour-consuming. Industrial practice…
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
Ning Wang, Bingkun Yao, Jie Zhou +4
Large language models (LLMs) have shown strong performance in Verilog generation from natural language description. However, ensuring the functional correctness of the generated co…
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
Junhao Ye, Yuchen Hu, Ke Xu +8
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology…
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Jie Zhou, Youshu Ji, Ning Wang +7
SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours…
UVLLM: An Automated Universal RTL Verification Framework using LLMs
Yuchen Hu, Junhao Ye, Ke Xu +11
Verifying hardware designs in embedded systems is crucial but often labor-intensive and time-consuming. While existing solutions have improved automation, they frequently rely on u…
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
Ning Wang, Bingkun Yao, Jie Zhou +3
Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Veril…
MEIC: Re-thinking RTL Debug Automation using LLMs
Ke Xu, Jialin Sun, Yuchen Hu +4
The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts.…