11 papers
Rethinking Unified Memory for NPU-PIM Systems: Dual-View Memory for Dynamic Inference of LLM
Shixin Zhao, Lian Liu, Tianhua Han +3
Heterogeneous architectures that combine neural processing unit (NPU) and processing-in-memory (PIM) are increasingly adopted to accelerate LLM inference. Prior work focuses on bui…
RTLCurator: Label-Efficient Data Curation for RTL Generation
Siyang Cai, Cangyuan Li, Wenjing Chang +4
Training large language models (LLMs) to write register-transfer level (RTL) requires large corpora of paired specifications and code, and such data is scarce enough that most publ…
CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heteroge…
When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification
Kun Wang, Cangyuan Li, Kaiyan Chang +3
The growing complexity of modern chips poses significant challenges to hardware verification. In recent years, coverage-guided fuzzing has emerged as a promising approach for impro…
Alpha-RTL: Test-Time Training for RTL Hardware Optimization
Peilong Zhou, Zhirong Chen, Cangyuan Li +4
Large language models (LLMs) have shown increasing promise in generating functionally correct register-transfer-level (RTL) hardware designs. Recent systems improve further through…
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
Zhirong Chen, Kaiyan Chang, Zhuolin Li +8
Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically…