30 citations · 31 across the 8 of their papers we have counts for
9 papers
pper and Lower Bounds for Blow-up Times in Coupled Reaction--Diffusion Systems with Nonlocal Sources
Xin Zhao, Aynuer Ailatusi, Xianfa Song +1
In this paper, we consider the following reaction-diffusion system \begin{equation*} \begin{cases} u_t=Δu+F\bigl(x,t,u,v,V(t)\bigr), & (x,t)\in\Om\times(0,T), v_t=Δv+G\bigl(x,t,u,v…
HiSparse: Scaling Sparse-Attention Decoding with Hierarchical KV Cache Management
Zhiqiang Xie, Zhangheng Huang, Tingwei Huang +3
Top-k sparse attention makes long-context LLM decoding cheap to compute: each step reads only a few thousand selected KV entries rather than the full context. Serving systems, howe…
HyperDFlash: Hyper-Connection-Aligned Block Speculative Decoding with Gated Residual Reduction
Luxi Lin, Shuang Peng, Rui Ma +7
We present HyperDFlash, a block-parallel speculative decoding framework tailored to DeepSeek-V4's Hyper-Connections (HC). Despite the strong performance of DeepSeek-V4's native Mul…
SAC: Disaggregated KV Cache System for Sparse Attention LLMs with CXL
Ruiyang Ma, Teng Ma, Junru Li +7
The scaling of LLMs toward long-context inference has shifted the primary serving system bottleneck from computation to memory capacity. Traditional solutions for dense attention m…
Pooling Engram Conditional Memory in Large Language Models using CXL
Ruiyang Ma, Teng Ma, Zhiyuan Su +11
Engram conditional memory has emerged as a promising component for LLMs by decoupling static knowledge lookup from dynamic computation. Since Engram exhibits sparse access patterns…
DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior
Ruiyang Ma, Yunhao Zhou, Yipeng Wang +9
There is a growing body of work on using Graph Neural Networks (GNNs) to learn representations of circuits, focusing primarily on their static characteristics. However, these model…
Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation
Ruiyang Ma, Daikang Kuang, Ziqian Liu +3
Debugging hardware designs requires significant manual effort during hardware development. After engineers identify a bug-triggering test case in simulation-based hardware verifica…
Bridging the Gap between Hardware Fuzzing and Industrial Verification
Ruiyang Ma, Tianhao Wei, Jiaxi Zhang +3
As hardware design complexity increases, hardware fuzzing emerges as a promising tool for automating the verification process. However, a significant gap still exists before it can…
VerilogReader: LLM-Aided Hardware Test Generation
Ruiyang Ma, Yuxin Yang, Ziqian Liu +4
Test generation has been a critical and labor-intensive process in hardware design verification. Recently, the emergence of Large Language Model (LLM) with their advanced understan…