7 citations · 7 across the 3 of their papers we have counts for
3 papers
eess.SP2025
Bridging the Initialization Gap: A Co-Optimization Framework for Mixed-Size Global Placement
Yuhao Ren, Yiting Liu, Yanfei Zhou +4
Global placement is a critical step with high computational complexity in VLSI physical design. Modern analytical placers formulate the placement problem as a nonlinear optimizatio…
cs.LG2025
The Power of Graph Signal Processing for Chip Placement Acceleration
Yiting Liu, Hai Zhou, Jia Wang +3
Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task,…
cs.LO2024★ 7 cited
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
Hongyang Pan, Cunqing Lan, Yiting Liu +5
A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages…