most citedA Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers

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cs.AR2025

Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs

He Jiang, Yi Guo, Shikai Guo +4

Timing optimization during global placement is critical for achieving optimal circuit performance and remains a key challenge in modern Field Programmable Gate Array (FPGA) design.…

cs.AR2024★ 2 cited

A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers

Zhihao Xu, Shikai Guo, Guilin Zhao +3

Field Programmable Gate Array (FPGA) logic synthesis compilers (e.g., Vivado, Iverilog, Yosys, and Quartus) are widely applied in Electronic Design Automation (EDA), such as the de…