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cs.AR2025
Sangam: Chiplet-Based DRAM-PIM Accelerator with CXL Integration for LLM Inferencing
Khyati Kiyawat, Zhenxing Fan, Yasas Seneviratne +5
Large Language Models (LLMs) are becoming increasingly data-intensive due to growing model sizes, and they are becoming memory-bound as the context length and, consequently, the ke…
cs.AR2025
Membrane: Accelerating Database Analytics with Bank-Level DRAM-PIM Filtering
Akhil Shekar, Kevin Gaffney, Martin Prammer +9
In-memory database query processing frequently involves substantial data transfers between the CPU and memory, leading to inefficiencies due to Von Neumann bottleneck. Processing-i…
cs.ET2025
Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache
Faaiq Waqar, Jungyoun Kwak, Junmo Lee +4
The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To…