2 papers
cs.LO2026
Fast Constraint Extraction for Corrective Control under STL Specifications via Logical Dependency Tracking
Antoine Besset, Joris Tillet, Chuchu Fan +1
Ensuring the satisfaction of Signal Temporal Logic (STL) specifications under uncertainty is challenging, as reachability-based monitoring provides guarantees but does not indicate…
cs.LO2025
Uncertainty Removal in Verification of Nonlinear Systems against Signal Temporal Logic via Incremental Reachability Analysis
Antoine Besset, Joris Tillet, Julien Alexandre dit Sandretto
A framework is presented for the verification of Signal Temporal Logic (STL) specifications over continuous-time nonlinear systems under uncertainty. Based on reachability analysis…