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cs.PL2025
SkyEgg: Heterogeneity-Aware Hardware Synthesis via Equality Saturation
Youwei Xiao, Yuyang Zou, Yun Liang +1
Hardware synthesis is a key interface between high-level programs and accelerator designs. Modern FPGAs increasingly expose heterogeneity in resource functionality and timing confi…
cs.PL2025
Cement2: Temporal Hardware Transactions for High-Level and Efficient FPGA Programming
Youwei Xiao, Zizhang Luo, Weijie Peng +2
Hardware design faces a fundamental challenge: raising abstraction to improve productivity while maintaining control over low-level details like cycle accuracy. Traditional RTL des…