11 papers
SPIMOE: Exploiting Hybrid Sparsity for Reasoning MoE Inference on Heterogeneous PIM Architectures
Rubing Yang, Cenlin Duan, Yingjie Qi +3
Long-reasoning Mixture-of-Experts (MoE) models expose two coupled inference bottlenecks: growing KV caches shift the critical path toward attention, while sparse expert activation…
PolyCIM: Improving Data Reuse in Digital CIM Accelerators with Polyhedral-Based Compilation
Yingjie Qi, Cenlin Duan, Yiou Wang +4
Digital Compute-in-Memory (CIM) presents a promising solution for accelerating deep neural networks (DNNs) through the integration of computational logic directly within memory arr…
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures
Yingjie Qi, Jianlei Yang, Rubing Yang +5
Compute-in-memory (CIM) has emerged as a pivotal direction for accelerating workloads in the field of machine learning, such as Deep Neural Networks (DNNs). However, the effective…
MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator
Xiaolin He, Cenlin Duan, Yingjie Qi +2
Computing-in-Memory (CIM) architectures have emerged as a promising solution for accelerating Deep Neural Networks (DNNs) by mitigating data movement bottlenecks. However, realizin…
ACE-GNN: Adaptive GNN Co-Inference with System-Aware Scheduling in Dynamic Edge Environments
Ao Zhou, Jianlei Yang, Tong Qiao +5
The device-edge co-inference paradigm effectively bridges the gap between the high resource demands of Graph Neural Networks (GNNs) and limited device resources, making it a promis…
HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference
Cenlin Duan, Jianlei Yang, Rubing Yang +8
The deployment of large language models (LLMs) presents significant challenges due to their enormous memory footprints, low arithmetic intensity, and stringent latency requirements…
Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity
Cenlin Duan, Jianlei Yang, Yikun Wang +7
Processing-in-memory (PIM) is a transformative architectural paradigm designed to overcome the Von Neumann bottleneck. Among PIM architectures, digital SRAM-PIM emerges as a promis…
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures
Yingjie Qi, Jianlei Yang, Yiou Wang +6
Digital Compute-in-Memory (CIM) architectures have shown great promise in Deep Neural Network (DNN) acceleration by effectively addressing the "memory wall" bottleneck. However, th…
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices
Ao Zhou, Jianlei Yang, Yingjie Qi +5
Graph Neural Networks (GNNs) are becoming increasingly popular for graph-based learning tasks such as point cloud processing due to their state-of-the-art (SOTA) performance. Never…
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity
Cenlin Duan, Jianlei Yang, Yiou Wang +7
Bit-level sparsity in neural network models harbors immense untapped potential. Eliminating redundant calculations of randomly distributed zero-bits significantly boosts computatio…
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory
Cenlin Duan, Jianlei Yang, Xiaolin He +9
Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been d…