4 papers
DTop-p MoE: Sparsity-Controlled Dynamic Top-p MoE for Foundation Model Pre-training
Can Jin, Hongwu Peng, Mingcan Xiang +7
Sparse Mixture-of-Experts architectures are essential for scaling model capacity efficiently, yet the standard Top- routing imposes a rigid sparsity pattern that ignores the int…
GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis
Kiran Thorat, Hongwu Peng, Yuebo Luo +8
Traditional verification methods in chip design are highly time-consuming and computationally demanding, especially for large scale circuits. Graph neural networks (GNNs) have gain…
LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
Kiran Thorat, Jiahui Zhao, Yaotian Liu +5
Large Language Models (LLMs) are gaining prominence in various fields, thanks to their ability to generate high- quality content from human instructions. This paper delves into the…
TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
Kiran Thorat, Amit Hasan, Caiwen Ding +1
Chip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being uti…