5 papers
GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis
Kiran Thorat, Hongwu Peng, Yuebo Luo +8
Traditional verification methods in chip design are highly time-consuming and computationally demanding, especially for large scale circuits. Graph neural networks (GNNs) have gain…
LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models
Kiran Thorat, Jiahui Zhao, Yaotian Liu +5
Large Language Models (LLMs) are gaining prominence in various fields, thanks to their ability to generate high- quality content from human instructions. This paper delves into the…
DR-CircuitGNN: Training Acceleration of Heterogeneous Circuit Graph Neural Network on GPUs
Yuebo Luo, Shiyang Li, Junran Tao +6
The increasing scale and complexity of integrated circuit design have led to increased challenges in Electronic Design Automation (EDA). Graph Neural Networks (GNNs) have emerged a…
TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
Kiran Thorat, Amit Hasan, Caiwen Ding +1
Chip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being uti…
HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
Jinwei Tang, Jiayin Qin, Kiran Thorat +5
With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL)…