2 papers
cs.ET2026
An FPGA-ASIC Co-Design Framework for Capacity-Constrained Physics-Based Ising Chips
Ruihong Yin, Yue Zheng, Chaohui Li +6
When a problem exceeds an analog Ising machine's spin capacity it cannot be solved in one shot: a digital orchestration layer must iteratively decompose the graph, clamp boundary s…
cs.ET2025
On the Limits of Ising Machines for Circuit-Derived SAT
Ahmet Efe, Hüsrev Cılasun, Abhimanyu Kumar +9
Emerging Ising machines are promising for solving computationally hard optimization problems, yet their limits on structured, circuit-derived satisfiability (SAT) problems remain p…