3 papers
cs.LG2025
ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
Bin Sun, Jingyi Zhou, Jianan Mu +5
In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-ne…
cs.AR2025
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
Zhiteng Chao, Yonghao Wang, Xinyu Zhang +9
Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog.…
cs.SE2025
Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware
Jianan Mu, Mingyu Shi, Yining Wang +5
LLM-based RTL generation is an interesting research direction, as it holds the potential to liberate the least automated stage in the current chip design. However, due to the subst…