1 citations · 1 across the 7 of their papers we have counts for
8 papers
ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
Bin Sun, Jingyi Zhou, Jianan Mu +5
In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-ne…
InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning
Bin Sun, Rengang Zhang, Zhiteng Chao +4
Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor…
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
Zhiteng Chao, Yonghao Wang, Xinyu Zhang +9
Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog.…
AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs
Hongqin Lyu, Yonghao Wang, Jiaxin Zhou +3
Assertion-based verification (ABV) is a key approach to checking whether a logic design complies with its architectural specifications. Existing assertion generation methods based…
AssertFix: Empowering Automated Assertion Fix via Large Language Models
Hongqin Lyu, Yunlin Du, Yonghao Wang +3
Assertion-based verification (ABV) is critical in ensuring that register-transfer level (RTL) designs conform to their functional specifications. SystemVerilog Assertions (SVA) eff…
AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging
Hongqin Lyu, Yonghao Wang, Yunlin Du +5
Assertion-based verification (ABV) serves as a crucial technique for ensuring that register-transfer level (RTL) designs adhere to their specifications. While Large Language Model…