12 citations · 13 across the 18 of their papers we have counts for
21 papers
E-ALS: Approximation-Potential-Aware E-Graph Rewriting for Approximate Logic Synthesis
Bin Sun, Jianan Mu, Jiaxi Zhang +4
Approximate logic synthesis (ALS) improves circuit power, performance, and area by trading exact correctness for bounded functional error. However, existing structural ALS methods…
ARMOR: Accelerating RTL Simulation by Mitigating the Front-End Bottleneck Using Node Compression
Jiaping Tang, Jianan Mu, Zhiteng Chao +3
RTL simulation is indispensable in chip design. High-performance simulators typically lower each node in the RTL graph into an instruction sequence. Although this per-node lowering…
An Efficient Fault-Tolerance Scheme for CKKS Computation on CPUs
Jianan Mu, Ge Yu, Tenghui Hua +6
Fully homomorphic encryption (FHE) enables computation on encrypted data, but its long ciphertext dataflow and high-dimensional modular arithmetic make it vulnerable to silent data…
HE^2: A Communication-Light Heterogeneous Architecture for Efficient Fully Homomorphic Encryption
Shangyi Shi, Husheng Han, Zhaoxuan Kan +8
CKKS, an emerging fully homomorphic encryption (FHE) scheme, has been promising in privacy-preserving applications by enabling SIMD fixed-point computations on ciphertexts. Despite…
AutoPPA: Automated Circuit PPA Optimization via Contrastive Code-based Rule Library Learning
Chongxiao Li, Pengwei Jin, Di Huang +14
Performance, power, and area (PPA) optimization is a fundamental task in RTL design, requiring a precise understanding of circuit functionality and the relationship between circuit…
Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction
Jiaping Tang, Jianan Mu, Tianyun Ma +3
Debugging represents a time-consuming and labor-intensive task in hardware design, with bug localization constituting a substantial portion of this process. While spectrum-based bu…
From Indiscriminate to Targeted: Functionally Critical Signal-Driven Assertion Generation using LLMs for Efficient RTL Verification
Yonghao Wang, Hongqin Lyu, Boling Chen +9
Functional verification has become the most time-consuming phase in IC development, and Assertion-Based Verification (ABV) is key to reducing debugging time. However, existing LLM-…
RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning
Xinyu Zhang, Zhiteng Chao, Yonghao Wang +6
Register Transfer Level (RTL) design translates high-level specifications into hardware using HDLs such as Verilog. Although LLM-based RTL generation is promising, the scarcity of…
On the Vulnerability of FHE Computation to Silent Data Corruption
Jianan Mu, Ge Yu, Zhaoxuan Kan +6
Fully Homomorphic Encryption (FHE) is rapidly emerging as a promising foundation for privacy-preserving cloud services, enabling computation directly on encrypted data. As FHE impl…
ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
Bin Sun, Jingyi Zhou, Jianan Mu +5
In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-ne…
InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning
Bin Sun, Rengang Zhang, Zhiteng Chao +4
Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor…
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
Zhiteng Chao, Yonghao Wang, Xinyu Zhang +9
Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog.…
Faver: Boosting LLM-based RTL Generation with Function Abstracted Verifiable Middleware
Jianan Mu, Mingyu Shi, Yining Wang +5
LLM-based RTL generation is an interesting research direction, as it holds the potential to liberate the least automated stage in the current chip design. However, due to the subst…
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule
Jiaping Tang, Jianan Mu, Zizhen Liu +6
With the rapid development of safety-critical applications such as autonomous driving and embodied intelligence, the functional safety of the corresponding electronic chips becomes…
FicGCN: Unveiling the Homomorphic Encryption Efficiency from Irregular Graph Convolutional Networks
Zhaoxuan Kan, Husheng Han, Shangyi Shi +5
Graph Convolutional Neural Networks (GCNs) have gained widespread popularity in various fields like personal healthcare and financial systems, due to their remarkable performance.…
Large Processor Chip Model
Kaiyan Chang, Mingzhi Chen, Yunji Chen +40
Computer System Architecture serves as a crucial bridge between software applications and the underlying hardware, encompassing components like compilers, CPUs, coprocessors, and R…
Extend IVerilog to Support Batch RTL Fault Simulation
Jiaping Tang, Jianan Mu, Zizhen Liu +3
The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure complian…
QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
Yaoyu Zhu, Di Huang, Hanqi Lyu +16
Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as…
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
Jiaping Tang, Jianan Mu, Silin Liu +8
As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric fo…
FlexMem: High-Parallel Near-Memory Architecture for Flexible Dataflow in Fully Homomorphic Encryption
Shangyi Shi, Husheng Han, Jianan Mu +7
Fully Homomorphic Encryption (FHE) imposes substantial memory bandwidth demands, presenting significant challenges for efficient hardware acceleration. Near-memory Processing (NMP)…
TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing
Husheng Han, Xinyao Zheng, Yuanbo Wen +11
Heterogeneous collaborative computing with NPU and CPU has received widespread attention due to its substantial performance benefits. To ensure data confidentiality and integrity d…